Cross-Scale Reliability Simulation of Chiplet Devices Based on Sub-Modeling Approach

As chip manufacturing processes continue to shrink to 3nm, the manufacturing difficulty and costs increase significantly while the yield rates decrease dramatically. Leveraging the advantages of heterogeneous integration, chiplet technology, which integrates chips with different process parameters from various manufacturers and fabrication nodes, has emerged as a crucial solution in the post-Moore era. However, the higher power density, increased interconnect density, and complex interconnect structures of chiplet devices pose severe reliability challenges. Additionally, the structural sizes within the devices often span three orders of magnitude, making rapid and accurate reliability assessments a challenging research problem. This study employs finite element simulation and the submodeling method to construct a cross-scale model for the overall chiplet device and it's C2 and C4 micro-interconnect solder joints, improving simulation efficiency. Subsequent simulations of powered thermal cycling were conducted and compared with standalone thermal cycling simulations. The results indicate that regions with concentrated chips lead to rapid temperature rises, and the Joule heating generated by the current primarily affects the plastic deformation process of the micro-interconnect solder joints. In chiplet devices, the plastic deformation of the C4 solder joints is significantly higher than that of the C2 solder joints. Finally, fatigue life predictions were conducted for both types of solder joints.