Correction to: A Memory Structure with Different Control Gates (Advanced Electronic Materials, (2018), 4, 7, (1800186), 10.1002/aelm.201800186)

Adv. Electron. Mater. 2018, 4, 1800186 DOI: 10.1002/aelm.201800186 In the original published article, Figures 2b and 4A with mistakes such as the wrong scale bar are shown. In the abstract the wrong quick response time was given. The correct sentence should read: Typical characterization of the memory device is also performed, and very quick response time (≈1-10 ns). Also the writing and reading time of ‘our design’ is incorrect in Table 1. The correct Figures 2b and 4 and Table 1 can be found below. 2 Figure (Figure presented.) b) Measured endurance property with a high on/off ratio as high as 10²–10⁵. Full sequences are repeated with 2 µs programming time. The wrong value is also given in the reference to figure 2 in the text on page 2. The correct sentence is: Figure 2b shows that this memory design could have a current on/off ratio in a range of 10²–10⁵. 4 Figure (Figure presented.) Characteristics of the memory with SnO control gate. a) Top view of this updated memory array with the CG junction. IGZO channel length/width is ≈30 µm/50 m. Scale bar = 20 µm. b) Transfer curves before and after erasing (VBG = −15 V, VCG = 15 V for ≈5 ms). c) Transfer curves before and after erasing (VBG = 5 V, VCG = −5 V for ≈5 ms). d) Retention time with longer than 1000 s after the first writing. 1 Table Comparison of the design here and typical memory designs (Table presented.) The authors apologies for any inconvenience this may have caused.