CMOS interface circuit for closed-loop accelerometer

An 18 V switched-capacitor CMOS interface circuit for the closed-loop operation of a capacitive accelerometer is designed. The circuit consists of a switched-capacitor charge sense amplifier, a PID control circuit and a correlated double sampling circuit. The effects of the 1/f noise of the amplifier and the offset voltage of an op-amp, as well as the kT/C charge noise from the parasitic capacitor are suppressed, by taking large area PMOS transistors at the Charge Sensing Amplifier (CSA) as an input stage and using a Correlated Double Sampling (CDS) technique and the 1/f noise, charge injection and clock feedthrough effects in the back-end circuits are eliminated by the technologies of high loop gain and force feedback. Moreover, the strong driving feedthrough is avoided by separating the drive and sense operations in the time domain by using the same electrodes. The designed complete chip with an area of 15.2 mm² is fabricated in a 2 μm two-metal and two-poly n-well CMOS and operated by a single 18 V supply, which can offer a measuring sensitivity of 420 mV/g and a noise of floor of 10 μg/√Hz in closed-loop.