Bug Hunting in the RISC-V SoC: The 1^st Integrated Circuit Security Challenge

Hardware security vulnerabilities pose a critical threat to modern system-on-chip (SoC) designs, yet their detection remains challenging due to low-level semantics and limited runtime observability. To address this gap, we organized the 1st Integrated Circuit Security Challenge (ICSC) in 2024, leveraging the open-source OpenPiton SoC platform. We introduced SecRisBen, a novel benchmark suite featuring realistic Register Transfer Level (RTL)-vulnerabilities systematically injected into the processor core and peripheral modules using five structured strategies. A multidimensional evaluation framework was developed to rigorously assess competing analysis tools. Two leading teams demonstrated state-of-the-art detection capabilities, employing information flow-based formal verification and semantic-driven property generation to uncover multiple high-impact vulnerabilities. The challenge successfully fostered collaboration and advancement in hardware security tools. Building on this momentum, we plan to hold subsequent competitions to further accelerate the progress in hardware security research and tool development.