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Bridgeless boost PFC with fast dynamic response algorithm

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In order to improve dynamic performance to load variation of PFC circuit, a digital PFC algorithm with fast dynamic response is proposed in bridgeless Boost PFC. The proposed algorithm improves dynamic response by increasing voltage loop bandwidth, and uses vector rotation scheme to generate compensating harmonic signal which counteracts second order harmonic resulted from increased voltage loop bandwidth. Without adding auxiliary circuit, the fast dynamic response digital algorithm is programmed with graphical approach which corresponds to control chip. Experimental results verify that the system has fast dynamic response when the load power varies in a large-scale, the power factor reaches 0.99 and input current total harmonic distortion (THD) is lower than 10%.

Original languageEnglish
Title of host publication2009 13th European Conference on Power Electronics and Applications, EPE '09
StatePublished - 2009
Event2009 13th European Conference on Power Electronics and Applications, EPE '09 - Barcelona, Spain
Duration: 8 Sep 200910 Sep 2009

Publication series

Name2009 13th European Conference on Power Electronics and Applications, EPE '09

Conference

Conference2009 13th European Conference on Power Electronics and Applications, EPE '09
Country/TerritorySpain
CityBarcelona
Period8/09/0910/09/09

Keywords

  • Fast dynamic response
  • Power factor correction
  • Vector rotation

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