Boosting SMT trace processors performance with data cache misssensitive thread scheduling mechanism

The penalty associated with data cache misses is one of the obstacles to the performance of SMT trace processors. The increased latency is not only required to resolve the missing data, the miss will also have negative impact on the PE resources utilization rate of the SMT trace processors. When data cache miss occurs in SMT trace processors, all the completed traces following the data-miss-trace (a trace with at least one data cache miss) will be delayed to commit for the data cache miss event. PE resources occupied by those traces can not be released until traces are committed, which wastes the PE execution resources and hampers the performance of SMT trace processors. In this paper, we propose several data cache miss sensitive thread scheduling mechanisms with the aim to tolerate the penalties of data cache misses. By choosing the thread wisely in trace dispatch and trace commit stages, the SMT trace processors performance can be improved further. Simulation results show that when using L1-L2 thread scheduling mechanism, performance will be improved by 2.8% (2-thread SMT trace processors), 8.0% (4-thread SMT trace processors) and 18.2% (8-thread SMT trace processors) with 8-PE, 512 KB L2 cache configuration.