Blind all-digital calibration of the second-order timing skew in TIADCs

Time-interleaved analog-to-digital converters (TIADCs) are widely adopted in high-speed measurement systems to overcome the sampling rate limitation of single-channel ADCs. However, channel mismatches, especially timing skew, introduce spectral spurs that severely degrade the signal-to-noise-and-distortion ratio (SNDR). This article proposes a fully digital background calibration method for compensating both first-order and residual second-order timing skew in TIADCs. By exploiting the Taylor series expansion of timing errors, the timing-induced distortion components are modeled as derivative-related replicas of the input signal. A Walsh-modulated adaptive noise cancellation architecture is then developed to decouple and suppress the timing-induced spurious components in the frequency domain. The proposed method operates blindly without requiring foreground calibration, additional reference channels, or trigonometric operations, making it suitable for streaming digital backend implementation. Simulation results demonstrate that the proposed second-order calibration effectively suppresses residual timing-induced spurs beyond conventional first-order calibration, leading to a significant SNDR improvement under practical non-ideal conditions. A fixed-point field-programmable gate array (FPGA) implementation on a ZCU106 platform further verifies the feasibility of the proposed method using pre-generated samples from a behavioral four-channel 12-bit TIADC model at an overall sampling rate of 2 GS/s, achieving an SNDR of 60.84 dB with moderate hardware complexity. The proposed approach provides an effective and hardware-efficient solution for enhancing the dynamic performance of high-speed TIADC-based measurement systems.