BIST technique of digital circuits based on improved tent chaotic sequence

This paper proposed a realization method of BIST technique of digital circuits based on improved Tent chaotic sequence to address the problem of testing digital circuits. Random sequence of ″0-1″ with white noise characteristics which generated by improved tent chaotic logistic map model hardware implementation is used as automatic test pattern generation (ATPG) of digital circuits. Test response signatures of chaotic sequence are obtained from CRC analysis of output response. It is shown that the method presented in this paper is easy for realization of BIST and has superior performance of higher rate of fault detection and fault isolation than that of M sequence. It is suitable for large-scale FPGA and automatic testing of other programmable logic circuits.