Analysis and Reduction Methods for Floating Potential and Voltage Stress in IPT System

In high-power inductive power transfer (IPT) systems, kilovolt-level winding voltages can induce hazardous floating potentials on ungrounded ferrites and aluminum shielding structures, thereby degrading insulation reliability and increasing the risk of electrical breakdown. To investigate this issue, a distributed-parameter model incorporating partial inductances and parasitic capacitances was developed to analyze the floating-potential coupling mechanism in magnetic couplers. Based on the proposed model, the effects of parasitic-capacitance distribution on floating potentials were investigated through finite-element analysis (FEA) and experiments. To intrinsically suppress floating potentials, a distributed compensation topology with a parallel-wound single-layer winding structure was proposed. By symmetrically balancing winding-terminal potentials and distributing compensation capacitors, the proposed topology significantly reduced floating potentials and winding voltage stress. Experimental results demonstrated that the ferrite and aluminum-shield potentials were reduced to 4% of the inverter output potential, the maximum ground-referenced voltage was reduced by 71%, and the winding-terminal voltage stress was reduced by 52%, accompanied by reduced dielectric loss associated with parasitic capacitive coupling. Experimental verification using an 80-kW prototype further confirmed the feasibility of the proposed method for high-power IPT systems.