TY - GEN
T1 - An ultra-low overhead LUT-based PUF for FPGA
AU - Wang, Jiadong
AU - Cui, Aijiao
AU - Li, Mengyang
AU - Qu, Gang
AU - Li, Huawei
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2017/1/26
Y1 - 2017/1/26
N2 - Physical unclonable function (PUF) utilizes the unexpected intrinsic manufacturing process variations of device to generate unique bit streams for authentication, key generation and random number generation. It has emerged as a promising primitive to address various challenges in hardware security. Traditional PUF schemes, such as arbiter PUF and ring oscillator (RO) PUF, do not have efficient implementations on FPGA and thus limit their usage as FPGA becomes the dominate design platform for today's emerging applications. In this paper, we propose a novel look-up table (LUT) shift register (SR) based PUF scheme for FPGA. This PUF incurs ultra1-low resource overhead, only two SLICEs to produce a 128-bit signature in our experimentation on XILINX Virtex-5 FPGA. Meanwhile, the PUF response are good in terms of uniqueness and robustness. At the same temperature, the proposed PUF has a 99%+ reliability on its response. When temperature changes between 25°C and 75°C, the robustness drops, but is still over 90%.
AB - Physical unclonable function (PUF) utilizes the unexpected intrinsic manufacturing process variations of device to generate unique bit streams for authentication, key generation and random number generation. It has emerged as a promising primitive to address various challenges in hardware security. Traditional PUF schemes, such as arbiter PUF and ring oscillator (RO) PUF, do not have efficient implementations on FPGA and thus limit their usage as FPGA becomes the dominate design platform for today's emerging applications. In this paper, we propose a novel look-up table (LUT) shift register (SR) based PUF scheme for FPGA. This PUF incurs ultra1-low resource overhead, only two SLICEs to produce a 128-bit signature in our experimentation on XILINX Virtex-5 FPGA. Meanwhile, the PUF response are good in terms of uniqueness and robustness. At the same temperature, the proposed PUF has a 99%+ reliability on its response. When temperature changes between 25°C and 75°C, the robustness drops, but is still over 90%.
KW - FPGA
KW - PUF
KW - look-up table
KW - shift register
UR - https://www.scopus.com/pages/publications/85015174071
U2 - 10.1109/AsianHOST.2016.7835554
DO - 10.1109/AsianHOST.2016.7835554
M3 - 会议稿件
AN - SCOPUS:85015174071
T3 - Proceedings of the 2016 IEEE Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2016
BT - Proceedings of the 2016 IEEE Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1st IEEE Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2016
Y2 - 19 December 2016 through 20 December 2016
ER -