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An MIV Test Method Using High-Precision Voltage Dividers

  • School of Electronics and Information Engineering, Harbin Institute of Technology

Research output: Contribution to journalArticlepeer-review

Abstract

Monolithic 3-D integration realizes the vertical interconnection between adjacent layers by using nanoscale monolithic intertier vias (MIVs). However, MIVs are particularly vulnerable to defects due to high integration density and substantial scaling of the interlayer dielectric. We propose a novel test method to detect open, short, and leakage faults in MIVs. Since the MIV defect will change its electrical characteristics, this method can test the MIV by identifying the voltage range divided according to different MIV faults. The effectiveness of fault detection is verified through HSPICE simulations. We also perform Monte Carlo simulations to prove the testability of the proposed method even in the case of process variations. Experimental results show that the proposed method has high detection precision while ensuring low hardware overhead.

Original languageEnglish
Pages (from-to)3240-3249
Number of pages10
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume43
Issue number10
DOIs
StatePublished - 2024
Externally publishedYes

Keywords

  • Fault models
  • monolithic 3-D integrated circuits (M3D ICs)
  • monolithic intertier vias (MIVs)
  • testing

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