An FPGA-based classification accelerator for embedded BCI system

Convolutional neural networks (CNNs) have catalyzed remarkable advancements in brain-computer interfaces (BCIs), laying a solid algorithmic foundation for real-time BCI systems on embedded devices. However, the limited memory and computational resources of edge devices severely impede CNN inference efficiency. Field-programmable gate arrays (FPGAs) have recently emerged as ideal accelerators, leveraging their inherent parallel processing capabilities to significantly boost model inference speed by optimizing convolutional operations. To address this challenge, we propose a holistic framework integrating a comprehensive model compression strategy with a high-efficiency FPGA-based acceleration architecture, which effectively balances hardware resource utilization and inference latency to meet the stringent real-time requirements of BCI systems. Experimental results show that our compressed model achieves a 5.41× compression ratio with a negligible accuracy drop of only 0.4%. When deployed on a Xilinx ZYNQ 7015 FPGA development board, the optimized model delivers ultra-low latency of merely 5.34 ms for BCI signal classification.