An automatic power estimation methodology for FPGA-based digital signal processing systems

With increasing design complexity of portable handheld devices, decreasing system power and energy consumption has become a key design metric. It is crucial for the designers to accurately evaluate the system power consumption in detail during the development process, especially for the power hungry digital system processing (DSP) system. This paper presents an automatic power estimation methodology, which can provide accurate dynamic power consumption distributions of DSP components implemented on Xilinx FPGAs. Additionally, the dependences of power consumption on system level parameters, including clock frequency, area utilization ratio and activity rate, are investigated from sensitivity metric. According to the experimental results, several power optimizations can be performed at the early stages of design flow.