An automated soft error rate analysis platform for combinational logic circuits

A novel SER analysis platform, called HSECT-ANLY, was developed to rapidly calculate the soft error rate (SER) of integrated circuits for the design of high reliable integrated circuits. HSECT-ANLY is suitable for the automated SER analysis of both the pure combinational logic circuits and the combinational part of sequential logic circuit. It uses accurate masking probability model to characterize the propagating of soft error glitches and uses input vector propagating and state probability propagating technique to overcome the deficiency of reconvergent paths with considerable speed gains. LL(k) syntax analysis technique is employed to parse the Verilog netlist to automate the analysis process and make the combinational part of sequential logic circuit analyzable. The platform was developed based on synthesized Verilog netlist and common standard cell library, which made it more practical than the other tools. By using HSECT-ANLY, experiments were carried out on ISCAS'85 and ISCAS'89 benchmark circuits and comparable results to the previous works were got with faster speed and more applicable circuit types. Experimental results show that the technique is appropriate to analyze the SER of module circuits and to direct the design of high reliability integrated circuits.