TY - GEN
T1 - A VLSI Implementation of Novel Neural Computing Unit
AU - Chen, Moran
AU - Wang, Mingjiang
AU - Liu, Hao
AU - Liu, Ming
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/23
Y1 - 2020/10/23
N2 - Since the application of artificial intelligence in speech recognition, image processing and other directions has become more and more widespread, the requirements of computer computing efficiency and power consumption performance have also been continuously increased. The main solution is combining traditional algorithms and artificial intelligence to solve this problem. However, this method cannot fundamentally solve the problem of insufficient computer performance. At the same time, due to the fact that the widely used neural units do not have enough biological neurological properties, artificial neurons do not have the ability of autonomous learning. In view of these issues and the information transfer process of biological neurons, a new hardware architecture for the basic neural unit in the neural network was proposed in this paper.
AB - Since the application of artificial intelligence in speech recognition, image processing and other directions has become more and more widespread, the requirements of computer computing efficiency and power consumption performance have also been continuously increased. The main solution is combining traditional algorithms and artificial intelligence to solve this problem. However, this method cannot fundamentally solve the problem of insufficient computer performance. At the same time, due to the fact that the widely used neural units do not have enough biological neurological properties, artificial neurons do not have the ability of autonomous learning. In view of these issues and the information transfer process of biological neurons, a new hardware architecture for the basic neural unit in the neural network was proposed in this paper.
KW - Izhikevich model
KW - biological neurology
KW - hardware design
KW - neural unit
UR - https://www.scopus.com/pages/publications/85101160409
U2 - 10.1109/ICSIP49896.2020.9339343
DO - 10.1109/ICSIP49896.2020.9339343
M3 - 会议稿件
AN - SCOPUS:85101160409
T3 - 2020 IEEE 5th International Conference on Signal and Image Processing, ICSIP 2020
SP - 348
EP - 353
BT - 2020 IEEE 5th International Conference on Signal and Image Processing, ICSIP 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th IEEE International Conference on Signal and Image Processing, ICSIP 2020
Y2 - 23 October 2020 through 25 October 2020
ER -