A VLSI architecture design of CAVLG decoder

Wu Di; Gao Wen; Mingzeng Hu; Zhenzhou Ji

doi:10.1109/ICASIC.2003.1277371

A VLSI architecture design of CAVLG decoder

Wu Di^*
, Gao Wen
, Mingzeng Hu
, Zhenzhou Ji

^*Corresponding author for this work

School of Computer Science and Technology (School of Software)

Harbin Institute of Technology
Academy of Science
Chinese Academy of Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

51 Scopus citations

Abstract

Variable length code is an integral component of many international standards on image and video compression. Recently, Context-based Adaptive Variable Length Coding (CAVLC) is adopted by the emerging JVT (also called H.264 in ITU. and AVC in MPEG-4). In this paper, we describe a novel architecture for CAVLC decoder, including a coeff_token decoder, level decoder, tolalzeros decoder and runbefore decoder. Together with a barrel shifter and controller, the pipeline architecture can decode every syntax element in one clock cycle. Therefore, it is very suitable for video applications that require high throughput.

Original language	English
Title of host publication	ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings
Editors	Ting-Ao Tang, Wenhong Li, Huihua Yu
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	962-965
Number of pages	4
ISBN (Electronic)	078037889X
DOIs	https://doi.org/10.1109/ICASIC.2003.1277371
State	Published - 2003
Event	5th International Conference on ASIC, ASICON 2003 - Beijing, China Duration: 21 Oct 2003 → 24 Oct 2003

Publication series

Name	IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings
Volume	2
ISSN (Print)	1523-553X

Conference

Conference	5th International Conference on ASIC, ASICON 2003
Country/Territory	China
City	Beijing
Period	21/10/03 → 24/10/03

Access to Document

10.1109/ICASIC.2003.1277371

Cite this

Di, W., Wen, G., Hu, M., & Ji, Z. (2003). A VLSI architecture design of CAVLG decoder. In T.-A. Tang, W. Li, & H. Yu (Eds.), ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings (pp. 962-965). Article 5733559 (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings; Vol. 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICASIC.2003.1277371

@inproceedings{6e149cfdee054710a1a02d5d90d8b9aa,

title = "A VLSI architecture design of CAVLG decoder",

abstract = "Variable length code is an integral component of many international standards on image and video compression. Recently, Context-based Adaptive Variable Length Coding (CAVLC) is adopted by the emerging JVT (also called H.264 in ITU. and AVC in MPEG-4). In this paper, we describe a novel architecture for CAVLC decoder, including a coeff\_token decoder, level decoder, tolalzeros decoder and runbefore decoder. Together with a barrel shifter and controller, the pipeline architecture can decode every syntax element in one clock cycle. Therefore, it is very suitable for video applications that require high throughput.",

author = "Wu Di and Gao Wen and Mingzeng Hu and Zhenzhou Ji",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE; 5th International Conference on ASIC, ASICON 2003 ; Conference date: 21-10-2003 Through 24-10-2003",

year = "2003",

doi = "10.1109/ICASIC.2003.1277371",

language = "英语",

series = "IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "962--965",

editor = "Ting-Ao Tang and Wenhong Li and Huihua Yu",

booktitle = "ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings",

address = "美国",

}

Di, W, Wen, G, Hu, M & Ji, Z 2003, A VLSI architecture design of CAVLG decoder. in T-A Tang, W Li & H Yu (eds), ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings., 5733559, IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 962-965, 5th International Conference on ASIC, ASICON 2003, Beijing, China, 21/10/03. https://doi.org/10.1109/ICASIC.2003.1277371

A VLSI architecture design of CAVLG decoder. / Di, Wu; Wen, Gao; Hu, Mingzeng et al.
ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings. ed. / Ting-Ao Tang; Wenhong Li; Huihua Yu. Institute of Electrical and Electronics Engineers Inc., 2003. p. 962-965 5733559 (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Variable length code is an integral component of many international standards on image and video compression. Recently, Context-based Adaptive Variable Length Coding (CAVLC) is adopted by the emerging JVT (also called H.264 in ITU. and AVC in MPEG-4). In this paper, we describe a novel architecture for CAVLC decoder, including a coeff_token decoder, level decoder, tolalzeros decoder and runbefore decoder. Together with a barrel shifter and controller, the pipeline architecture can decode every syntax element in one clock cycle. Therefore, it is very suitable for video applications that require high throughput.

AB - Variable length code is an integral component of many international standards on image and video compression. Recently, Context-based Adaptive Variable Length Coding (CAVLC) is adopted by the emerging JVT (also called H.264 in ITU. and AVC in MPEG-4). In this paper, we describe a novel architecture for CAVLC decoder, including a coeff_token decoder, level decoder, tolalzeros decoder and runbefore decoder. Together with a barrel shifter and controller, the pipeline architecture can decode every syntax element in one clock cycle. Therefore, it is very suitable for video applications that require high throughput.

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Di W, Wen G, Hu M, Ji Z. A VLSI architecture design of CAVLG decoder. In Tang TA, Li W, Yu H, editors, ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2003. p. 962-965. 5733559. (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings). doi: 10.1109/ICASIC.2003.1277371

A VLSI architecture design of CAVLG decoder

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