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A VLSI architecture design of 1-D DWT

  • Zhiyang Cao*
  • , Zhenzhou Ji
  • , Mingzeng Hu
  • *Corresponding author for this work
  • Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

Abstract

In the paper, we design an efficiently, scalable one-dimensional discrete wavelet transform (1-D DWT) architecture. The architecture is constructed with cascaded basic computation units, which implement multiplication, accumulation and down-sampling functions. The architecture is quite regular and scalable so that it fits into a VLSI implementation and can be extended to an arbitrary 1D-DWT with L taps and J octaves.

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
EditorsXingming Zhou, Ming Xu, Stefan Jahnichen, Jiannong Cao
PublisherSpringer Verlag
Pages104-108
Number of pages5
ISBN (Print)3540200541, 9783540200543
DOIs
StatePublished - 2003

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2834
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

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