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A variable-length FFT processor base on mixed-radix algorithm for PAPR reduction in OFDM systems

  • Xiangbin Meng*
  • , Jinxiang Wang
  • , Hailong Yan
  • *Corresponding author for this work
  • Harbin Institute of Technology
  • Shenyang Institute of Engineering

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An attractive technique of variable-length Fast Fourier transform (FFT) processor is proposed for PAPR reduction in orthogonal frequency division multiplexing (OFDM) systems. Mixed-radix algorithm and single path delay feedback (SDF) pipeline architecture is adopted to obtain low computation complexity and preferable flexibility for its VLSI implementation. The FFT processor can be reconfigured as 512, 1024, 2048, 4096-points, moreover, the only one RAM unit is used for store sine/cosine tables. The chip is mapped to the 0.18μm CMOS technology and the core area is 7.896mm2. The experiment results show that the proposed FFT processor is suitable for PAPR reduction in OFDM communication systems.

Original languageEnglish
Title of host publicationAdvances in Mechanics Engineering
Pages826-829
Number of pages4
DOIs
StatePublished - 2012
Event2012 International Conference on Advances in Mechanics Engineering, ICAME 2012 - , Hong Kong
Duration: 3 Aug 20125 Aug 2012

Publication series

NameAdvanced Materials Research
Volume588-589
ISSN (Print)1022-6680

Conference

Conference2012 International Conference on Advances in Mechanics Engineering, ICAME 2012
Country/TerritoryHong Kong
Period3/08/125/08/12

Keywords

  • FFT processor
  • OFDM
  • PAPR
  • SDF

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