A SMT-ARM simulator and performance evaluation

Exponential growth in the number of on-chip transistors with smaller size, make each generation of embedded microprocessors capable to supply more processing ability. In this paper a microarchitecture approach is proposed to make a simultaneous multithreading extension on ARM ISA processor. By exploiting both Instruction Level Parallelism and Thread Level Parallelism, the architecture can be expected to achieve better tradeoff between performance and hardware cost. The organization of the architecture is described. Detailed simulations of microarchitecture show IPC is improved with the multithreading extension of the simplesim-arm architecture greatly, especially for some benchmark combination.