A SiC MOSFET accelerated degradation test platform that accounts for turn-on and turn-off times

As the demand for applications and technological advancements continues to rise, the performance of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) has been subject to ongoing optimization. Nevertheless, in practical implementations, SiC MOSFETs encounter various reliability challenges, one of the most pressing being the issue of alternating current bias temperature instability (AC BTI). The turn-on and turn-off times of SiC MOSFETs exhibit sensitivity to AC BTI. During degradation assessments, significant alterations in these timing parameters a re observed throughout the degradation process, which subsequently influences the degradation rate and presents difficulties regarding stress stability in accelerated testing scenarios. To mitigate this issue, the present study proposes the development of a self-regulating gate drive resistance platform aimed at maintaining the stability of the turn-on and turn-off times of SiC MOSFETs during accelerated testing conditions. An examination of strategies for preserving the consistency of on-off timing in accelerated degradation testing.