A scheduling and partitioning scheme for low power circuit operating at multiple voltages

Ling Wang; H. Selvaraj

doi:10.1109/dsd.2003.1231915

A scheduling and partitioning scheme for low power circuit operating at multiple voltages

Ling Wang
, H. Selvaraj

University of Nevada, Las Vegas

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, a scheme is presented to minimize power dissipation through scheduling and partitioning at the behavior level with resources operating at multiple voltages. The scheme uses partitioning to preserve locality in the assignment of operations to hardware units. Experimental results show that the proposed method can efficiently reduce power.

Original language	English
Title of host publication	Proceedings - Euromicro Symposium on Digital System Design, DSD 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	144-147
Number of pages	4
ISBN (Electronic)	0769520030, 9780769520032
DOIs	https://doi.org/10.1109/dsd.2003.1231915
State	Published - 2003
Externally published	Yes
Event	Euromicro Symposium on Digital System Design, DSD 2003 - Belek-Antalya, Turkey Duration: 1 Sep 2003 → 6 Sep 2003

Publication series

Name	Proceedings - Euromicro Symposium on Digital System Design, DSD 2003

Conference

Conference	Euromicro Symposium on Digital System Design, DSD 2003
Country/Territory	Turkey
City	Belek-Antalya
Period	1/09/03 → 6/09/03

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10.1109/dsd.2003.1231915

Cite this

Wang, L., & Selvaraj, H. (2003). A scheduling and partitioning scheme for low power circuit operating at multiple voltages. In Proceedings - Euromicro Symposium on Digital System Design, DSD 2003 (pp. 144-147). (Proceedings - Euromicro Symposium on Digital System Design, DSD 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/dsd.2003.1231915

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title = "A scheduling and partitioning scheme for low power circuit operating at multiple voltages",

abstract = "In this paper, a scheme is presented to minimize power dissipation through scheduling and partitioning at the behavior level with resources operating at multiple voltages. The scheme uses partitioning to preserve locality in the assignment of operations to hardware units. Experimental results show that the proposed method can efficiently reduce power.",

author = "Ling Wang and H. Selvaraj",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; Euromicro Symposium on Digital System Design, DSD 2003 ; Conference date: 01-09-2003 Through 06-09-2003",

year = "2003",

doi = "10.1109/dsd.2003.1231915",

language = "英语",

series = "Proceedings - Euromicro Symposium on Digital System Design, DSD 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "144--147",

booktitle = "Proceedings - Euromicro Symposium on Digital System Design, DSD 2003",

address = "美国",

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Wang, L & Selvaraj, H 2003, A scheduling and partitioning scheme for low power circuit operating at multiple voltages. in Proceedings - Euromicro Symposium on Digital System Design, DSD 2003. Proceedings - Euromicro Symposium on Digital System Design, DSD 2003, Institute of Electrical and Electronics Engineers Inc., pp. 144-147, Euromicro Symposium on Digital System Design, DSD 2003, Belek-Antalya, Turkey, 1/09/03. https://doi.org/10.1109/dsd.2003.1231915

A scheduling and partitioning scheme for low power circuit operating at multiple voltages. / Wang, Ling; Selvaraj, H.
Proceedings - Euromicro Symposium on Digital System Design, DSD 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 144-147 (Proceedings - Euromicro Symposium on Digital System Design, DSD 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A scheduling and partitioning scheme for low power circuit operating at multiple voltages

AU - Wang, Ling

AU - Selvaraj, H.

PY - 2003

Y1 - 2003

N2 - In this paper, a scheme is presented to minimize power dissipation through scheduling and partitioning at the behavior level with resources operating at multiple voltages. The scheme uses partitioning to preserve locality in the assignment of operations to hardware units. Experimental results show that the proposed method can efficiently reduce power.

AB - In this paper, a scheme is presented to minimize power dissipation through scheduling and partitioning at the behavior level with resources operating at multiple voltages. The scheme uses partitioning to preserve locality in the assignment of operations to hardware units. Experimental results show that the proposed method can efficiently reduce power.

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DO - 10.1109/dsd.2003.1231915

M3 - 会议稿件

AN - SCOPUS:29844432066

T3 - Proceedings - Euromicro Symposium on Digital System Design, DSD 2003

SP - 144

EP - 147

BT - Proceedings - Euromicro Symposium on Digital System Design, DSD 2003

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - Euromicro Symposium on Digital System Design, DSD 2003

Y2 - 1 September 2003 through 6 September 2003

ER -

A scheduling and partitioning scheme for low power circuit operating at multiple voltages

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