A research on subsection progressive optimization placement algorithm of FPGA

Xiu Hai Cui; Hai Gang Yang; Xiao Gong; Juan Huang; Yi Tao Tan

doi:10.3724/SP.J.1146.2008.01689

A research on subsection progressive optimization placement algorithm of FPGA

Xiu Hai Cui
, Hai Gang Yang^*
, Xiao Gong
, Juan Huang
, Yi Tao Tan

^*Corresponding author for this work

CAS - Institute of Electronics
University of Chinese Academy of Sciences

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

A novel FPGA simulated annealing placement algorithm is proposed to improve the routability and optimize the length of wires. Different cost functions are applied to different temperature range. In high temperature stage, the half perimeter method is utilized to fast optimize the placement; while in low temperature stage, a variable factor is added into the cost function and the reasonable temper process is also used to improve the quality of placement. Experiment results demonstrate that, compared with the VPR, the proposed method requires 6% fewer routing tracks and the length of wire is 4~23% shorter.

Original language	English
Pages (from-to)	1395-1400
Number of pages	6
Journal	Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology
Volume	32
Issue number	6
DOIs	https://doi.org/10.3724/SP.J.1146.2008.01689
State	Published - Jun 2010
Externally published	Yes

Keywords

Cost function
FPGA
Pacement
Routability
Simulated annealing
VPR (Versatile Place and Route)

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10.3724/SP.J.1146.2008.01689

Cite this

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title = "A research on subsection progressive optimization placement algorithm of FPGA",

abstract = "A novel FPGA simulated annealing placement algorithm is proposed to improve the routability and optimize the length of wires. Different cost functions are applied to different temperature range. In high temperature stage, the half perimeter method is utilized to fast optimize the placement; while in low temperature stage, a variable factor is added into the cost function and the reasonable temper process is also used to improve the quality of placement. Experiment results demonstrate that, compared with the VPR, the proposed method requires 6\% fewer routing tracks and the length of wire is 4\textasciitilde{}23\% shorter.",

keywords = "Cost function, FPGA, Pacement, Routability, Simulated annealing, VPR (Versatile Place and Route)",

author = "Cui, \{Xiu Hai\} and Yang, \{Hai Gang\} and Xiao Gong and Juan Huang and Tan, \{Yi Tao\}",

year = "2010",

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doi = "10.3724/SP.J.1146.2008.01689",

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T1 - A research on subsection progressive optimization placement algorithm of FPGA

AU - Cui, Xiu Hai

AU - Yang, Hai Gang

AU - Gong, Xiao

AU - Huang, Juan

AU - Tan, Yi Tao

PY - 2010/6

Y1 - 2010/6

N2 - A novel FPGA simulated annealing placement algorithm is proposed to improve the routability and optimize the length of wires. Different cost functions are applied to different temperature range. In high temperature stage, the half perimeter method is utilized to fast optimize the placement; while in low temperature stage, a variable factor is added into the cost function and the reasonable temper process is also used to improve the quality of placement. Experiment results demonstrate that, compared with the VPR, the proposed method requires 6% fewer routing tracks and the length of wire is 4~23% shorter.

AB - A novel FPGA simulated annealing placement algorithm is proposed to improve the routability and optimize the length of wires. Different cost functions are applied to different temperature range. In high temperature stage, the half perimeter method is utilized to fast optimize the placement; while in low temperature stage, a variable factor is added into the cost function and the reasonable temper process is also used to improve the quality of placement. Experiment results demonstrate that, compared with the VPR, the proposed method requires 6% fewer routing tracks and the length of wire is 4~23% shorter.

KW - Cost function

KW - FPGA

KW - Pacement

KW - Routability

KW - Simulated annealing

KW - VPR (Versatile Place and Route)

UR - https://www.scopus.com/pages/publications/77954363252

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JF - Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology

IS - 6

ER -

A research on subsection progressive optimization placement algorithm of FPGA

Abstract

Keywords

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