A pseudo-pipelined VLSI architecture of two elliptic curve scalar multiplications

Wang Xu; Zhang Yan

doi:10.1109/EDSSC.2009.5394270

A pseudo-pipelined VLSI architecture of two elliptic curve scalar multiplications

Wang Xu^*
, Zhang Yan

^*Corresponding author for this work

Harbin Institute of Technology Shenzhen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Two elliptic curve scalar multiplications (ECMLT) are used in some important elliptic curve encryption algorithms, a pseudo-pipelined VLSI architecture of two ECMLTs over GF(2^m) is proposed for these algorithms. The proposed architecture includes three word-serial finite field (FF) multipliers, and each FF multiplier has word size w. Implemented using FPGA, two ECMLTs are computed in approximately 4⌈m/w⌉(m-l) clock cycles in the proposed architecture. Compared with the architectures proposed by other authors recently, it is shown that the computation time for two ECMLTs is the shortest by using our proposed architecture.

Original language	English
Title of host publication	2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009
Pages	258-261
Number of pages	4
DOIs	https://doi.org/10.1109/EDSSC.2009.5394270
State	Published - 2009
Externally published	Yes
Event	2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009 - Xi'an, China Duration: 25 Dec 2009 → 27 Dec 2009

Publication series

Name	2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009

Conference

Conference	2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009
Country/Territory	China
City	Xi'an
Period	25/12/09 → 27/12/09

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10.1109/EDSSC.2009.5394270

Cite this

Xu, W., & Yan, Z. (2009). A pseudo-pipelined VLSI architecture of two elliptic curve scalar multiplications. In 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009 (pp. 258-261). Article 5394270 (2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009). https://doi.org/10.1109/EDSSC.2009.5394270

@inproceedings{ab1a80b3e32e40f2bbaacd6ab88d8698,

title = "A pseudo-pipelined VLSI architecture of two elliptic curve scalar multiplications",

abstract = "Two elliptic curve scalar multiplications (ECMLT) are used in some important elliptic curve encryption algorithms, a pseudo-pipelined VLSI architecture of two ECMLTs over GF(2m) is proposed for these algorithms. The proposed architecture includes three word-serial finite field (FF) multipliers, and each FF multiplier has word size w. Implemented using FPGA, two ECMLTs are computed in approximately 4⌈m/w⌉(m-l) clock cycles in the proposed architecture. Compared with the architectures proposed by other authors recently, it is shown that the computation time for two ECMLTs is the shortest by using our proposed architecture.",

author = "Wang Xu and Zhang Yan",

year = "2009",

doi = "10.1109/EDSSC.2009.5394270",

language = "英语",

isbn = "9781424442980",

series = "2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009",

pages = "258--261",

booktitle = "2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009",

note = "2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009 ; Conference date: 25-12-2009 Through 27-12-2009",

}

Xu, W & Yan, Z 2009, A pseudo-pipelined VLSI architecture of two elliptic curve scalar multiplications. in 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009., 5394270, 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009, pp. 258-261, 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009, Xi'an, China, 25/12/09. https://doi.org/10.1109/EDSSC.2009.5394270

A pseudo-pipelined VLSI architecture of two elliptic curve scalar multiplications. / Xu, Wang; Yan, Zhang.
2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009. 2009. p. 258-261 5394270 (2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Two elliptic curve scalar multiplications (ECMLT) are used in some important elliptic curve encryption algorithms, a pseudo-pipelined VLSI architecture of two ECMLTs over GF(2m) is proposed for these algorithms. The proposed architecture includes three word-serial finite field (FF) multipliers, and each FF multiplier has word size w. Implemented using FPGA, two ECMLTs are computed in approximately 4⌈m/w⌉(m-l) clock cycles in the proposed architecture. Compared with the architectures proposed by other authors recently, it is shown that the computation time for two ECMLTs is the shortest by using our proposed architecture.

AB - Two elliptic curve scalar multiplications (ECMLT) are used in some important elliptic curve encryption algorithms, a pseudo-pipelined VLSI architecture of two ECMLTs over GF(2m) is proposed for these algorithms. The proposed architecture includes three word-serial finite field (FF) multipliers, and each FF multiplier has word size w. Implemented using FPGA, two ECMLTs are computed in approximately 4⌈m/w⌉(m-l) clock cycles in the proposed architecture. Compared with the architectures proposed by other authors recently, it is shown that the computation time for two ECMLTs is the shortest by using our proposed architecture.

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BT - 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009

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Y2 - 25 December 2009 through 27 December 2009

ER -

A pseudo-pipelined VLSI architecture of two elliptic curve scalar multiplications

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