A Planar Transformer Integration Design With 2D Scalability for Vertical Power Delivery to HPC Processors

Driven by AI training, the power consumption and current required by high-performance computing (HPC) processors are increasing. This is causing changes in the power supply architecture and current delivery structure of HPC processors. The existing LLC DCX design based on LPD structure has only one-dimensional (1-D) scalability and has not considered integrating the output terminals into the transformer, which will be detrimental to its application in the future VPD. In this article, a planar transformer integration design with 2-D scalability for vertical power delivery to HPC processors is proposed. A VPD structure is first introduced to explain the necessity of the proposed matrix transformer integration design approach. Then, it is demonstrated how to integrate the output terminals into the transformer and realize the 2-D seamless expansion of the transformer, which facilitates its application in the VPD structure and is compatible with the LPD design. A transformer design example and its footprint and loss optimization are also conducted. Finally, an 810 W prototype was built and tested, achieving a peak efficiency of 94.4% and a transformer power density of 1660 W/in3, which has a higher power density compared with the existing state-of-art DCX designs.