A perceptron-based replication scheme for managing the shared last level cache

The shared last level cache (SLLC), which provides large effective cache capacity, is widely adopted in modern chip multiprocessors (CMPs). But, long on-chip access latency in the SLLC is a key problem that hurts system performance. Replication is an effective way to relieve this problem through storing a replica of L1 victims in the near local LLC slice. However, previous replication schemes either blindly create replicas based on no feature of cache blocks or select replicas based on a single feature (such as data type, access count, etc.), which will affect the replication accuracy and limit the system performance improvements. In this paper, according to the successful application of machine learning (ML) in the field of computer architecture optimization in recent years, we develop a novel perceptron-based replication scheme (PBR) for effectively managing the SLLC in CMPs. Unlike existing single-feature-based schemes, this scheme effectively combines four features related to the reuse behavior of L1 victims, which are address (Addr), program counter (PC), data type (DT), and access count (AC), through perceptron to facilitate the accuracy of replica selection. Experimental results show that compared with the two previously proposed single-feature-based replication schemes: ASR and LADR, PBR decreases the execution time by 6.59% and 18.27%, and reduces the network traffic by 10.35% and 13.18% respectively with negligible energy consumption, hardware and area overhead.