A novel two-dimensional error correction code for multiple bit upsets mitigation in memories

A novel two-dimensional error codes correction circuit which can effectively mitigate radiation-induced MBU in memory is proposed in this paper. The key features of the proposed method are that it can correct MBU with any possible width and assure the reliability of memory with very low cost overhead. Firstly, the proposed two-dimensional error codes are constructed in the paper. A word in memory is transformed to a matrix form. Low complexity multibit error detection codes are applied in each row for error detection while parity codes are applied in each column for error correction. Then, the correction algorithm of memory against MBU is proposed in the paper. Finally, the circuit and its layout design of the proposed method are implemented. A method called layout partition is proposed to mitigate MBU in the redundancy bits of the two-dimensional error correction code to further improve the reliability of memory. The experimental results reveal that the proposed method has a higher reliability. Compared with the existing multibit error correction codes, it has lower encoding and decoding overheads, even for Hamming codes.