TY - GEN
T1 - A novel low-cost interface design for SystemC and SystemVerilog Co-simulation
AU - Zhu, Yunzhong
AU - Li, Tao
AU - Guo, Jingpeng
AU - Zhou, Haiyang
AU - Fu, Fangfa
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/7/21
Y1 - 2016/7/21
N2 - Based on the high-level abstract golden model in SystemC and UVM in SystemVerilog, the Co-simulation method can effectively reduce the complexity of SoC verification. But how to design the interface between the two languages is the key to improve the efficiency of verification. A novel interface based on DPI is proposed in the paper. The interface adopts a two-stage structure and includes an environmental configuration unit and a protocol conversion unit. They are respectively realized in the two languages domains. Furthermore, to increase the simulation speed, the timing synchronization unit and stimulus import unit are realized in SystemC domain. The experiment results show that under the same configuring conditions and same test stimulus, compared to UVMC co-simulation library provided by Mentor Company, the interface proposed by this paper has same functional coverage while simulation time is reduced by about 20%, which has a significant advantage in performance.
AB - Based on the high-level abstract golden model in SystemC and UVM in SystemVerilog, the Co-simulation method can effectively reduce the complexity of SoC verification. But how to design the interface between the two languages is the key to improve the efficiency of verification. A novel interface based on DPI is proposed in the paper. The interface adopts a two-stage structure and includes an environmental configuration unit and a protocol conversion unit. They are respectively realized in the two languages domains. Furthermore, to increase the simulation speed, the timing synchronization unit and stimulus import unit are realized in SystemC domain. The experiment results show that under the same configuring conditions and same test stimulus, compared to UVMC co-simulation library provided by Mentor Company, the interface proposed by this paper has same functional coverage while simulation time is reduced by about 20%, which has a significant advantage in performance.
UR - https://www.scopus.com/pages/publications/84982256744
U2 - 10.1109/ASICON.2015.7516907
DO - 10.1109/ASICON.2015.7516907
M3 - 会议稿件
AN - SCOPUS:84982256744
T3 - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
BT - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
A2 - Ren, Junyan
A2 - Tang, Ting-Ao
A2 - Ye, Fan
A2 - Yu, Huihua
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
Y2 - 3 November 2015 through 6 November 2015
ER -