@inproceedings{3a746cde91234da193c204d06706b006,
title = "A new hardware architecture for H.264 intra prediction frame processing",
abstract = "This paper presents a hardware architecture for H.264 intra prediction frame processing. This design reuse some modules according to the common parts of luma 16X16 prediction and chroma 8X8 prediction in architecture and algorithm. Thereby reduces the area of chip and cost, and enhances its market competition. The parallel pipeline is also adopted to enhance the encode efficiency. The top-down design method is adopted in this design. In the beginning the system architecture and C model are designed. Then we implemented the architecture by Verilog HDL. After the ASIC synthesis, which is based on Chartered 0.13um technology library, it can run 1080P@30 under the clock frequency 102M with 386.46K logic gates. The result of simulation and synthesis show that the timing and area requirement of design are both capable for 1080P@30fps HD applications.",
keywords = "ASIC, H.264, intra prediction, quantization",
author = "Xu Shou-Gen and Wang Ming-Jiang and Zuo Shi-Kai",
year = "2011",
doi = "10.1109/IMSAA.2011.6156344",
language = "英语",
isbn = "9781457713286",
series = "2011 IEEE 5th International Conference on Internet Multimedia Systems Architecture and Application, IMSAA 2011 - Conference Proceedings",
booktitle = "2011 IEEE 5th International Conference on Internet Multimedia Systems Architecture and Application, IMSAA 2011 - Conference Proceedings",
note = "2011 IEEE 5th International Conference on Internet Multimedia Systems Architecture and Application, IMSAA 2011 ; Conference date: 12-12-2011 Through 13-12-2011",
}