A Network-on-Chip Accelerator for Genome Variant Analysis

Recent advances in high-throughput genome sequencing provide unprecedented opportunities for characterizing individual genomic landscapes and identifying mutations relevant to diagnosis and therapy and also bring exponentially growing sequence data. They, thus, pose a huge challenge for accessing the large amounts of genomic data with low latency in high-performance computing. Many analysis tools pursue high-performance with fine-grain parallelism based on chip many-core processors (CMP) which integrates a large number of cores in a single die. With an ever increasing number of on-chip cores, Network-on-Chip (NoC) which carries all the processing data and interactive messages connects them together. The low latency and high throughput NoC has become the main challenge of accelerating genome variant analysis in the big data era. In this work, we propose a lightweight low-latency NoC microarchitecture. It adds a ring-subnetwork on a mesh-subnetwork to transmit conflicting packets and simplify router pipeline stages of the mesh-subnetwork. The experiment shows that the NoC accelerator improves data transmission greatly. On a range of genome variant analysis applications, it improves runtime by 1.08× on average.