A multi-functional floating point multiplier

De Liu; Mingjiang Wang; Yiwen Wang; Hang Su

doi:10.1109/ICASID.2015.7405661

A multi-functional floating point multiplier

De Liu^*
, Mingjiang Wang
, Yiwen Wang
, Hang Su

^*Corresponding author for this work

Harbin Institute of Technology Shenzhen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper presents a multi-functional double precision floating-point multiplier design. The proposed design can perform one double precision multiplication or one vector multiplication of two 2D vectors which is consist of single precision floating-point numbers. The proposed design is modeled in Verilog-HDL and verified through extensive functional simulation. The presented multi-functional double-precision multiplier is compared with conventional single and double precision multipliers by ASIC synthesis. The functionality of supporting single precision multiplication is at the cost of 8% more area and 9% more delay, compared to a conventional double precision multiplier. Compared to the combination of one double and four single precision multipliers, the proposed design saves 47% area.

Original language	English
Title of host publication	Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015
Publisher	IEEE Computer Society
Pages	56-60
Number of pages	5
ISBN (Electronic)	9781467371391
DOIs	https://doi.org/10.1109/ICASID.2015.7405661
State	Published - 11 Feb 2016
Externally published	Yes
Event	9th IEEE International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015 - Xiamen, China Duration: 25 Sep 2015 → 27 Sep 2015

Publication series

Name	Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID
Volume	2016-February
ISSN (Print)	2163-5048
ISSN (Electronic)	2163-5056

Conference

Conference	9th IEEE International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015
Country/Territory	China
City	Xiamen
Period	25/09/15 → 27/09/15

Keywords

floating point arithmetic
multi-functional multiplier

Access to Document

10.1109/ICASID.2015.7405661

Cite this

Liu, D., Wang, M., Wang, Y., & Su, H. (2016). A multi-functional floating point multiplier. In Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015 (pp. 56-60). Article 7405661 (Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID; Vol. 2016-February). IEEE Computer Society. https://doi.org/10.1109/ICASID.2015.7405661

@inproceedings{24478fcfa23a4937aef8163aac368246,

title = "A multi-functional floating point multiplier",

abstract = "This paper presents a multi-functional double precision floating-point multiplier design. The proposed design can perform one double precision multiplication or one vector multiplication of two 2D vectors which is consist of single precision floating-point numbers. The proposed design is modeled in Verilog-HDL and verified through extensive functional simulation. The presented multi-functional double-precision multiplier is compared with conventional single and double precision multipliers by ASIC synthesis. The functionality of supporting single precision multiplication is at the cost of 8\% more area and 9\% more delay, compared to a conventional double precision multiplier. Compared to the combination of one double and four single precision multipliers, the proposed design saves 47\% area.",

keywords = "floating point arithmetic, multi-functional multiplier",

author = "De Liu and Mingjiang Wang and Yiwen Wang and Hang Su",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 9th IEEE International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015 ; Conference date: 25-09-2015 Through 27-09-2015",

year = "2016",

month = feb,

day = "11",

doi = "10.1109/ICASID.2015.7405661",

language = "英语",

series = "Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID",

publisher = "IEEE Computer Society",

pages = "56--60",

booktitle = "Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015",

address = "美国",

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Liu, D, Wang, M, Wang, Y & Su, H 2016, A multi-functional floating point multiplier. in Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015., 7405661, Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID, vol. 2016-February, IEEE Computer Society, pp. 56-60, 9th IEEE International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015, Xiamen, China, 25/09/15. https://doi.org/10.1109/ICASID.2015.7405661

A multi-functional floating point multiplier. / Liu, De; Wang, Mingjiang; Wang, Yiwen et al.
Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015. IEEE Computer Society, 2016. p. 56-60 7405661 (Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID; Vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A multi-functional floating point multiplier

AU - Liu, De

AU - Wang, Mingjiang

AU - Wang, Yiwen

AU - Su, Hang

PY - 2016/2/11

Y1 - 2016/2/11

N2 - This paper presents a multi-functional double precision floating-point multiplier design. The proposed design can perform one double precision multiplication or one vector multiplication of two 2D vectors which is consist of single precision floating-point numbers. The proposed design is modeled in Verilog-HDL and verified through extensive functional simulation. The presented multi-functional double-precision multiplier is compared with conventional single and double precision multipliers by ASIC synthesis. The functionality of supporting single precision multiplication is at the cost of 8% more area and 9% more delay, compared to a conventional double precision multiplier. Compared to the combination of one double and four single precision multipliers, the proposed design saves 47% area.

AB - This paper presents a multi-functional double precision floating-point multiplier design. The proposed design can perform one double precision multiplication or one vector multiplication of two 2D vectors which is consist of single precision floating-point numbers. The proposed design is modeled in Verilog-HDL and verified through extensive functional simulation. The presented multi-functional double-precision multiplier is compared with conventional single and double precision multipliers by ASIC synthesis. The functionality of supporting single precision multiplication is at the cost of 8% more area and 9% more delay, compared to a conventional double precision multiplier. Compared to the combination of one double and four single precision multipliers, the proposed design saves 47% area.

KW - floating point arithmetic

KW - multi-functional multiplier

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DO - 10.1109/ICASID.2015.7405661

M3 - 会议稿件

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BT - Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015

PB - IEEE Computer Society

T2 - 9th IEEE International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015

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ER -

Liu D, Wang M, Wang Y, Su H. A multi-functional floating point multiplier. In Proceedings of 2015 IEEE 9th International Conference on Anti-Counterfeiting, Security and Identification, ASID 2015. IEEE Computer Society. 2016. p. 56-60. 7405661. (Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID). doi: 10.1109/ICASID.2015.7405661

A multi-functional floating point multiplier

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