A mixed-signal simulator for VHDL-AMS

Liyi Xiao; Bin Li; Yizheng Ye; Guoyong Huang; Jinjun Guo; Peng Zhang

doi:10.1109/ASPDAC.2001.913320

A mixed-signal simulator for VHDL-AMS

Liyi Xiao
, Bin Li
, Yizheng Ye
, Guoyong Huang
, Jinjun Guo
, Peng Zhang

School of Astronautics

Harbin Institute of Technology
China Huada Integrated Circuit Design Center

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Capable and efficient simulators are in demand for designing complex analog and mixed-signal circuits and systems. With the standardization of VHDL-AMS, the demand is being realized. VHDL-AMS is an analog and mixed-signal extension to VHDL. This paper introduces a mixed-signal simulator for it. The simulator was developed on the original VHDL digital simulation environment. An analog kernel has been integrated into the environment for the simulation of the continuous behavior of a model. The paper presents the algorithms adopted in the analog kernel and the synchronization of the digital and analog executions. The performance of the simulator is examined by mixed-signal examples.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2001
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2001
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	287-291
Number of pages	5
ISBN (Electronic)	0780366336
DOIs	https://doi.org/10.1109/ASPDAC.2001.913320
State	Published - 2001
Event	Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan Duration: 30 Jan 2001 → 2 Feb 2001

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2001-January

Conference

Conference	Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
Country/Territory	Japan
City	Yokohama
Period	30/01/01 → 2/02/01

Keywords

Circuit simulation
Circuits and systems
Continuous time systems
Design engineering
Digital simulation
Integrated circuit synthesis
Kernel
Microelectronics
Missiles
Standardization

Access to Document

10.1109/ASPDAC.2001.913320

Cite this

Xiao, L., Li, B., Ye, Y., Huang, G., Guo, J., & Zhang, P. (2001). A mixed-signal simulator for VHDL-AMS. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001 (pp. 287-291). Article 913320 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2001.913320

@inproceedings{015c7459a2a34d0a997261bd2f44953b,

title = "A mixed-signal simulator for VHDL-AMS",

abstract = "Capable and efficient simulators are in demand for designing complex analog and mixed-signal circuits and systems. With the standardization of VHDL-AMS, the demand is being realized. VHDL-AMS is an analog and mixed-signal extension to VHDL. This paper introduces a mixed-signal simulator for it. The simulator was developed on the original VHDL digital simulation environment. An analog kernel has been integrated into the environment for the simulation of the continuous behavior of a model. The paper presents the algorithms adopted in the analog kernel and the synchronization of the digital and analog executions. The performance of the simulator is examined by mixed-signal examples.",

keywords = "Circuit simulation, Circuits and systems, Continuous time systems, Design engineering, Digital simulation, Integrated circuit synthesis, Kernel, Microelectronics, Missiles, Standardization",

author = "Liyi Xiao and Bin Li and Yizheng Ye and Guoyong Huang and Jinjun Guo and Peng Zhang",

note = "Publisher Copyright: {\textcopyright} 2001 IEEE.; Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 ; Conference date: 30-01-2001 Through 02-02-2001",

year = "2001",

doi = "10.1109/ASPDAC.2001.913320",

language = "英语",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "287--291",

booktitle = "Proceedings of the ASP-DAC 2001",

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Xiao, L, Li, B, Ye, Y, Huang, G, Guo, J & Zhang, P 2001, A mixed-signal simulator for VHDL-AMS. in Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001., 913320, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2001-January, Institute of Electrical and Electronics Engineers Inc., pp. 287-291, Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001, Yokohama, Japan, 30/01/01. https://doi.org/10.1109/ASPDAC.2001.913320

A mixed-signal simulator for VHDL-AMS. / Xiao, Liyi; Li, Bin; Ye, Yizheng et al.
Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., 2001. p. 287-291 913320 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Capable and efficient simulators are in demand for designing complex analog and mixed-signal circuits and systems. With the standardization of VHDL-AMS, the demand is being realized. VHDL-AMS is an analog and mixed-signal extension to VHDL. This paper introduces a mixed-signal simulator for it. The simulator was developed on the original VHDL digital simulation environment. An analog kernel has been integrated into the environment for the simulation of the continuous behavior of a model. The paper presents the algorithms adopted in the analog kernel and the synchronization of the digital and analog executions. The performance of the simulator is examined by mixed-signal examples.

KW - Circuit simulation

KW - Circuits and systems

KW - Continuous time systems

KW - Design engineering

KW - Digital simulation

KW - Integrated circuit synthesis

KW - Kernel

KW - Microelectronics

KW - Missiles

KW - Standardization

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Xiao L, Li B, Ye Y, Huang G, Guo J, Zhang P. A mixed-signal simulator for VHDL-AMS. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc. 2001. p. 287-291. 913320. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2001.913320

A mixed-signal simulator for VHDL-AMS

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Keywords

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