A LXI bus interface hardware design method with the SOPC

Zhaoqing Liu; Yu Peng; Liyan Qiao

doi:10.1109/AUTEST.2007.4374260

A LXI bus interface hardware design method with the SOPC

Zhaoqing Liu^*
, Yu Peng
, Liyan Qiao

^*Corresponding author for this work

School of Electronics and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

A hardware design method of LXI bus interface using FPGA-based SOPC is presented in this paper. The NIOSII core from Altera™ was taken to implement the control logic of the LXI C-Class interface. And the DPE-1588IP core was chosen to achieve the design of LXI B-class interface, in which the IEEE 1588 high-precision time protocol required by the specifications was realized. While such a B-class interface is connected to an industry standard Gigabit Ethernet PHY device, Gigabit network speed suggested in the LXI specifications can be reached. As for the hardware trigger bus of the LXI A-class interface, the SN65MLVD200A was adopted to make half-duplex, M-LVDS trigger bus interface. Besides the above functions, the NIOS core can also be used to control the functional circuit in LXI devices.

Original language	English
Title of host publication	IEEE AUTOTESTCON 2007
Subtitle of host publication	Systems Readiness Technology Conference, Proceedings - Transforming Maintenance: Closing the Loop Between ATE and Integrated Diagnostics
Pages	504-510
Number of pages	7
DOIs	https://doi.org/10.1109/AUTEST.2007.4374260
State	Published - 2007
Event	42nd Annual IEEE AUTOTESTCON Conference 2007 - Baltimore, MD, United States Duration: 17 Sep 2007 → 20 Sep 2007

Publication series

Name	AUTOTESTCON (Proceedings)

Conference

Conference	42nd Annual IEEE AUTOTESTCON Conference 2007
Country/Territory	United States
City	Baltimore, MD
Period	17/09/07 → 20/09/07

Keywords

Hardware trigger
IEEE 1588
MLVDS
NIOS II
SOPC

Access to Document

10.1109/AUTEST.2007.4374260

Cite this

@inproceedings{51bfb9d6f13544288b6cee016b378dd5,

title = "A LXI bus interface hardware design method with the SOPC",

abstract = "A hardware design method of LXI bus interface using FPGA-based SOPC is presented in this paper. The NIOSII core from Altera{\texttrademark} was taken to implement the control logic of the LXI C-Class interface. And the DPE-1588IP core was chosen to achieve the design of LXI B-class interface, in which the IEEE 1588 high-precision time protocol required by the specifications was realized. While such a B-class interface is connected to an industry standard Gigabit Ethernet PHY device, Gigabit network speed suggested in the LXI specifications can be reached. As for the hardware trigger bus of the LXI A-class interface, the SN65MLVD200A was adopted to make half-duplex, M-LVDS trigger bus interface. Besides the above functions, the NIOS core can also be used to control the functional circuit in LXI devices.",

keywords = "Hardware trigger, IEEE 1588, MLVDS, NIOS II, SOPC",

author = "Zhaoqing Liu and Yu Peng and Liyan Qiao",

year = "2007",

doi = "10.1109/AUTEST.2007.4374260",

language = "英语",

isbn = "1424412390",

series = "AUTOTESTCON (Proceedings)",

pages = "504--510",

booktitle = "IEEE AUTOTESTCON 2007",

note = "42nd Annual IEEE AUTOTESTCON Conference 2007 ; Conference date: 17-09-2007 Through 20-09-2007",

}

Liu, Z , Peng, Y & Qiao, L 2007, A LXI bus interface hardware design method with the SOPC. in IEEE AUTOTESTCON 2007: Systems Readiness Technology Conference, Proceedings - Transforming Maintenance: Closing the Loop Between ATE and Integrated Diagnostics., 4374260, AUTOTESTCON (Proceedings), pp. 504-510, 42nd Annual IEEE AUTOTESTCON Conference 2007, Baltimore, MD, United States, 17/09/07. https://doi.org/10.1109/AUTEST.2007.4374260

A LXI bus interface hardware design method with the SOPC. / Liu, Zhaoqing ; Peng, Yu ; Qiao, Liyan.
IEEE AUTOTESTCON 2007: Systems Readiness Technology Conference, Proceedings - Transforming Maintenance: Closing the Loop Between ATE and Integrated Diagnostics. 2007. p. 504-510 4374260 (AUTOTESTCON (Proceedings)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A hardware design method of LXI bus interface using FPGA-based SOPC is presented in this paper. The NIOSII core from Altera™ was taken to implement the control logic of the LXI C-Class interface. And the DPE-1588IP core was chosen to achieve the design of LXI B-class interface, in which the IEEE 1588 high-precision time protocol required by the specifications was realized. While such a B-class interface is connected to an industry standard Gigabit Ethernet PHY device, Gigabit network speed suggested in the LXI specifications can be reached. As for the hardware trigger bus of the LXI A-class interface, the SN65MLVD200A was adopted to make half-duplex, M-LVDS trigger bus interface. Besides the above functions, the NIOS core can also be used to control the functional circuit in LXI devices.

AB - A hardware design method of LXI bus interface using FPGA-based SOPC is presented in this paper. The NIOSII core from Altera™ was taken to implement the control logic of the LXI C-Class interface. And the DPE-1588IP core was chosen to achieve the design of LXI B-class interface, in which the IEEE 1588 high-precision time protocol required by the specifications was realized. While such a B-class interface is connected to an industry standard Gigabit Ethernet PHY device, Gigabit network speed suggested in the LXI specifications can be reached. As for the hardware trigger bus of the LXI A-class interface, the SN65MLVD200A was adopted to make half-duplex, M-LVDS trigger bus interface. Besides the above functions, the NIOS core can also be used to control the functional circuit in LXI devices.

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KW - SOPC

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T2 - 42nd Annual IEEE AUTOTESTCON Conference 2007

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ER -

A LXI bus interface hardware design method with the SOPC

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