A low static-power instruction Cache based on farthermost block pair

Aiming at the requirement of reducing the increasing static-power consumption caused by the on-chip caches, a low static-power instruction cache architecture called FBPC, which was based on the farthermost block pairs, was presented. Due to the high temporal locality and spatial locality of reference in instruction address streams, the instructions far away from the current address are unlikely to be referenced in the near future. Based on this observation, with the modification on data array, FBPC can find the farthermost block pairs that are supposed unlikely to be referenced, and put them into low-power sleep mode to save the static-power consumption. Experiments on 11 SPEC2000 benchmarks showed that FBPC could reduce the static-power consumption efficiently.