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A low power deterministic test pattern generator for BIST based on cellular automata

  • Bei Cao*
  • , Liyi Xiao
  • , Yongsheng Wang
  • *Corresponding author for this work
  • Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The test pattern generator (TPG) in deterministic BIST often suffers from some problems such as extra test power consumption, area overhead and idle test cycles. In this paper, an efficient algorithm is proposed to synthesize a built-in TPG from low power deterministic test patterns without inserting any redundancy test vectors. The structure of TPG is based on the non-uniform cellular automata (CA) and is used to test combinational circuits. And the algorithm is based on the nearest neighborhood model, which can find an optimal non-uniform CA topology to generate given low power test patterns. Simulation results using benchmark combinational circuits show that the generator is efficient to generate the deterministic test patterns in terms of power consumption, area overhead and test time.

Original languageEnglish
Title of host publicationProceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Pages266-269
Number of pages4
DOIs
StatePublished - 2008
Event4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 - Hong Kong, SAR, Hong Kong
Duration: 23 Jan 200825 Jan 2008

Publication series

NameProceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008

Conference

Conference4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Country/TerritoryHong Kong
CityHong Kong, SAR
Period23/01/0825/01/08

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