A low latency kernel recursive least squares processor using FPGA technology

Yeyong Pang; Shaojun Wang; Yu Peng; Nicholas J. Fraser; Philip H.W. Leong

doi:10.1109/FPT.2013.6718345

A low latency kernel recursive least squares processor using FPGA technology

Yeyong Pang
, Shaojun Wang
, Yu Peng
, Nicholas J. Fraser
, Philip H.W. Leong

School of Electronics and Information Engineering

Harbin Institute of Technology
The University of Sydney

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Scopus citations

Abstract

The kernel recursive least squares (KRLS) algorithm performs non-linear regression in an online manner, with similar computational requirements to linear techniques. In this paper, an implementation of the KRLS algorithm utilising pipelining and vectorisation for performance; and microcoding for reusability is described. The design can be scaled to allow tradeoffs between capacity, performance and area. Compared with a central processing unit (CPU) and digital signal processor (DSP), the processor improves on execution time, latency and energy consumption by factors of 5, 5 and 12 respectively.

Original language	English
Title of host publication	FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology
Pages	144-151
Number of pages	8
DOIs	https://doi.org/10.1109/FPT.2013.6718345
State	Published - 2013
Event	2013 12th International Conference on Field-Programmable Technology, FPT 2013 - Kyoto, Japan Duration: 9 Dec 2013 → 11 Dec 2013

Publication series

Name	FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology

Conference

Conference	2013 12th International Conference on Field-Programmable Technology, FPT 2013
Country/Territory	Japan
City	Kyoto
Period	9/12/13 → 11/12/13

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/FPT.2013.6718345

Cite this

Pang, Y., Wang, S., Peng, Y., Fraser, N. J., & Leong, P. H. W. (2013). A low latency kernel recursive least squares processor using FPGA technology. In FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology (pp. 144-151). Article 6718345 (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology). https://doi.org/10.1109/FPT.2013.6718345

@inproceedings{50c5ef1e22a94ebb913e14308b4ea882,

title = "A low latency kernel recursive least squares processor using FPGA technology",

abstract = "The kernel recursive least squares (KRLS) algorithm performs non-linear regression in an online manner, with similar computational requirements to linear techniques. In this paper, an implementation of the KRLS algorithm utilising pipelining and vectorisation for performance; and microcoding for reusability is described. The design can be scaled to allow tradeoffs between capacity, performance and area. Compared with a central processing unit (CPU) and digital signal processor (DSP), the processor improves on execution time, latency and energy consumption by factors of 5, 5 and 12 respectively.",

author = "Yeyong Pang and Shaojun Wang and Yu Peng and Fraser, \{Nicholas J.\} and Leong, \{Philip H.W.\}",

year = "2013",

doi = "10.1109/FPT.2013.6718345",

language = "英语",

isbn = "9781479921990",

series = "FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology",

pages = "144--151",

booktitle = "FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology",

note = "2013 12th International Conference on Field-Programmable Technology, FPT 2013 ; Conference date: 09-12-2013 Through 11-12-2013",

}

Pang, Y, Wang, S, Peng, Y, Fraser, NJ & Leong, PHW 2013, A low latency kernel recursive least squares processor using FPGA technology. in FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology., 6718345, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology, pp. 144-151, 2013 12th International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, 9/12/13. https://doi.org/10.1109/FPT.2013.6718345

A low latency kernel recursive least squares processor using FPGA technology. / Pang, Yeyong; Wang, Shaojun; Peng, Yu et al.
FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. 2013. p. 144-151 6718345 (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Peng, Yu

AU - Fraser, Nicholas J.

AU - Leong, Philip H.W.

PY - 2013

Y1 - 2013

N2 - The kernel recursive least squares (KRLS) algorithm performs non-linear regression in an online manner, with similar computational requirements to linear techniques. In this paper, an implementation of the KRLS algorithm utilising pipelining and vectorisation for performance; and microcoding for reusability is described. The design can be scaled to allow tradeoffs between capacity, performance and area. Compared with a central processing unit (CPU) and digital signal processor (DSP), the processor improves on execution time, latency and energy consumption by factors of 5, 5 and 12 respectively.

AB - The kernel recursive least squares (KRLS) algorithm performs non-linear regression in an online manner, with similar computational requirements to linear techniques. In this paper, an implementation of the KRLS algorithm utilising pipelining and vectorisation for performance; and microcoding for reusability is described. The design can be scaled to allow tradeoffs between capacity, performance and area. Compared with a central processing unit (CPU) and digital signal processor (DSP), the processor improves on execution time, latency and energy consumption by factors of 5, 5 and 12 respectively.

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DO - 10.1109/FPT.2013.6718345

M3 - 会议稿件

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SN - 9781479921990

T3 - FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology

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BT - FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology

T2 - 2013 12th International Conference on Field-Programmable Technology, FPT 2013

Y2 - 9 December 2013 through 11 December 2013

ER -

Pang Y, Wang S, Peng Y, Fraser NJ, Leong PHW. A low latency kernel recursive least squares processor using FPGA technology. In FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. 2013. p. 144-151. 6718345. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology). doi: 10.1109/FPT.2013.6718345

A low latency kernel recursive least squares processor using FPGA technology

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UN SDGs

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