@inproceedings{34817f5b2466475d8b7d2c44416d2179,
title = "A Hardware Security Evaluation Platform on RISC-V SoC",
abstract = "The escalating complexity of integrated circuits (ICs) enables a substantial computational power, yet also results in a challenging verification of vulnerability. Effective and efficient verification of ICs in a high design complexity turns to a great concern to be solved. This paper presents a hardware security evaluation platform constructed on the open-source RISC-V System-on-Chip (SoC) - OpenPiton to facilitate the development of the techniques on design vulnerability discovery. Some pertinent hardware vulnerabilities are compiled and integrated into both the processor core and the peripheral modules of the OpenPiton hardware platform.",
keywords = "Hardware Security, Hardware Vulnerabilities, OpenPiton, RISC-V, SoC",
author = "Xiaolong Cheng and Aijiao Cui and Yier Jin",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 8th IEEE International Test Conference in Asia, ITC-Asia 2024 ; Conference date: 18-08-2024 Through 20-08-2024",
year = "2024",
doi = "10.1109/ITC-Asia62534.2024.10661352",
language = "英语",
series = "Proceedings - ITC-Asia 2024: 8th IEEE International Test Conference in Asia",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings - ITC-Asia 2024",
address = "美国",
}