Abstract
There has been recent interest on designing double error correction (DEC) codes for 32-bit data words that support fast decoding as they can be useful to protect memories. To that end, solutions based on orthogonal Latin square codes have been recently presented that achieve fast decoding but require a large number of parity check bits. In this letter, a DEC code derived from difference set codes is presented. The proposed code is able to reduce the number of parity check bits needed at the cost of a slightly more complex decoding. Therefore, it provides memory designers with an additional option that can be useful when making trade-offs between memory size and speed.
| Original language | English |
|---|---|
| Pages (from-to) | 125-127 |
| Number of pages | 3 |
| Journal | IEEE Transactions on Device and Materials Reliability |
| Volume | 18 |
| Issue number | 1 |
| DOIs | |
| State | Published - Mar 2018 |
Keywords
- Error correction codes
- difference set codes
- memories
- orthogonal Latin square codes
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