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A DLL-TDC Circuit with Calibration Network

  • School of Information Science and Engineering, Harbin Institute of Technology Weihai
  • Shandong Jiao Tong University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper introduces a DLL-TDC circuit with a calibration neural network to address the issue of uneven delay time distribution across each delay unit of the TDC. Following the integration of the DLL circuit into the TDC for the purpose of average calibration, this paper also proposes the construction of a neural network model which purpose of this is to calculate the accurate delay time of each delay unit. Furthermore, the neural network model can also replace the repetitive code density measurement work in order to complete bin-by-bin calibration. The neural network model has an accuracy rate of over 91%.

Original languageEnglish
Title of host publication2025 4th International Symposium on Computer Applications and Information Technology, ISCAIT 2025
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1273-1277
Number of pages5
ISBN (Electronic)9798331542856
DOIs
StatePublished - 2025
Externally publishedYes
Event4th International Symposium on Computer Applications and Information Technology, ISCAIT 2025 - Xi'an, China
Duration: 21 Mar 202523 Mar 2025

Publication series

Name2025 4th International Symposium on Computer Applications and Information Technology, ISCAIT 2025

Conference

Conference4th International Symposium on Computer Applications and Information Technology, ISCAIT 2025
Country/TerritoryChina
CityXi'an
Period21/03/2523/03/25

Keywords

  • application-specific integrated circuit
  • delay-locked loop
  • neural network
  • time-digital converter

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