A Deadbeat Digital Current Controller Based on Parallel Disturbance Rejection Structure for SPMSM

In the field of surface-mounted permanent magnet synchronous motor (SPMSM) drive, deadbeat predictive current control (DPCC) can achieve high dynamic response, but its poor antidisturbance performance limits the application. To address this problem, a deadbeat digital current controller with a parallel disturbance rejection structure is proposed in this article. In the proposed scheme, the disturbance control loop is organized by the deadbeat frequency characteristics, current reference, and a disturbance controller so that it can eliminate the time lag in disturbance estimation. Thus, the proposed parallel antidisturbance structure can achieve better dynamic performance of disturbance estimation than traditional linear observers. The disturbance controller in the control loop is designed based on the internal model control (IMC) method. To further enhance periodic disturbance suppression capability, a Repetitive-IMC control law is further adopted in the disturbance controller. By employing linear control theory, the coefficients related to the proposed scheme can be easily designed in the frequency domain. Compared with other advanced digital current controller with deadbeat response, the antidisturbance performance evaluation is carried out. Finally, the experiment proves the effectiveness of this method.