A CMOS interface circuit for piezoresistive accelerometer

The non-ideal effect generated by piezoresistive accelerometer with Favors Stone electric bridge structure has a sever negative effect on the performance of the whole system. How to suppress or compensate this non-ideal effect with the interface circuit attracts great attention but remains a big challenge. A novel interface circuit for piezoresistive accelerometer which calibrates zero offset of the sensor is designed for this aim. It is based on successive approximation. Comparer, counter and DAC are adopted to reduce the offset of the system and to enhance dynamic range. Trans-conductance with capacitances feedback compensation technology is used in the design of low-power three-stage amplifier to reduce the power consumption of the system. The power of counter and comparer is cut off after auto-zeroing to further reduce power dissipation. The circuit is fabricated with 0.5μm CMOS standard process. The testing results exhibit a max auto-zeroing voltage of 500mV, with 4mV resolution and 4.62mW power consumption.