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A calculation model of ground bounce effect in power gating circuits

  • Liyi Xiao*
  • , Yu Sun
  • , Bo Zhang
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Power gating is one of the most effective techniques to reduce the growing leakage power in the CMOS integrated circuits. However, during the turn on progress of the power gated circuits, ground bounce effect appears which will cause voltage fluctuations on the ground line within the chip through the parasitic parameters of package. In this paper, an analytical model is proposed to calculate the voltage fluctuations, and this model can be used to estimate the maximum and period of the fluctuations. A standard CMOS 90nm process is used to validate the model. Experimental results show that the errors of the period and maximum peak value of the voltage fluctuation are 10.18% and 9.98% on average compared with the SPICE simulation. The runtime could be greatly reduced.

Original languageEnglish
Title of host publication2011 Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2011
Pages324-327
Number of pages4
DOIs
StatePublished - 2011
Event2011 Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2011 - Harbin, China
Duration: 12 Oct 201116 Oct 2011

Publication series

Name2011 Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2011

Conference

Conference2011 Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2011
Country/TerritoryChina
CityHarbin
Period12/10/1116/10/11

Keywords

  • ground bounce model
  • low power
  • power gating
  • voltage fluctuation

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