A 5V 124.92dB SNR discrete-time CMOS delta-sigma ADC with integrator sharing

This paper presents the design and implementation of a third-order sigma-delta modulator (SDM) with a 3-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) as a multi-bit quantizer, targeting high-precision medical instrumentation with a 24-bit resolution. The proposed architecture leverages an oversampling rate of 256 to enhance resolution and mitigate noise. To minimize power consumption, an integrator reuse technique is employed, significantly reducing the power overhead typically associated with multi-stage integration in high-order SDM M designs. The use of a 3-bit SAR ADC enables a high-resolution quantization while maintaining low static power consumption, which is crucial for portable medical devices. The resulting SDM system achieves a Signal-to-Noise Ratio (SNR) of 124.92 dB and an Effective Number of Bits (ENOB) of 20.46, demonstrating its capability to meet the stringent performance requirements of high-precision medical applications. The proposed design offers an efficient balance between power consumption and accuracy, making it suitable for integration into low-power, high-performance medical instrumentation requiring 24-bit ADC precision.