A 12.5Gbps Dual Loop CDR with Multi-band VCO and Novel Frequency Band Switch

Weijia Han; Yongsheng Wang; Jinxiang Wang

doi:10.1109/ICSICT.2018.8564977

A 12.5Gbps Dual Loop CDR with Multi-band VCO and Novel Frequency Band Switch

Weijia Han
, Yongsheng Wang
, Jinxiang Wang

School of Astronautics

Harbin Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

A novel 12.5Gbps quarter rate CDR is presented in this paper. For lock acquisition depends on the frequency tracking loop (FLL loop) and recovered clock jitter depends on the phase tracking loop (PLL loop) without one impacting the other, the CDR gets both short lock acquisition and low clock jitter. Moreover, a novel frequency band switch (FBS) is proposed, which switches the band of VCO. Meanwhile, the FBS ensures proper switching of dual loops to prevent false locking, without another lock detector, reducing the power consumption. Realized in 55-nm CMOS technology, the CDR consumes 15.2mW with a 1.2V supply.

Original language	English
Title of host publication	2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings
Editors	Ting-Ao Tang, Fan Ye, Yu-Long Jiang
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538644409
DOIs	https://doi.org/10.1109/ICSICT.2018.8564977
State	Published - 5 Dec 2018
Event	14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Qingdao, China Duration: 31 Oct 2018 → 3 Nov 2018

Publication series

Name	2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings

Conference

Conference	14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018
Country/Territory	China
City	Qingdao
Period	31/10/18 → 3/11/18

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10.1109/ICSICT.2018.8564977

Cite this

Han, W., Wang, Y., & Wang, J. (2018). A 12.5Gbps Dual Loop CDR with Multi-band VCO and Novel Frequency Band Switch. In T.-A. Tang, F. Ye, & Y.-L. Jiang (Eds.), 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings Article 8564977 (2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSICT.2018.8564977

Han, Weijia ; Wang, Yongsheng ; Wang, Jinxiang. / A 12.5Gbps Dual Loop CDR with Multi-band VCO and Novel Frequency Band Switch. 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings. editor / Ting-Ao Tang ; Fan Ye ; Yu-Long Jiang. Institute of Electrical and Electronics Engineers Inc., 2018. (2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings).

@inproceedings{b8223690cd7242fe881ea6ee2e03833b,

title = "A 12.5Gbps Dual Loop CDR with Multi-band VCO and Novel Frequency Band Switch",

abstract = "A novel 12.5Gbps quarter rate CDR is presented in this paper. For lock acquisition depends on the frequency tracking loop (FLL loop) and recovered clock jitter depends on the phase tracking loop (PLL loop) without one impacting the other, the CDR gets both short lock acquisition and low clock jitter. Moreover, a novel frequency band switch (FBS) is proposed, which switches the band of VCO. Meanwhile, the FBS ensures proper switching of dual loops to prevent false locking, without another lock detector, reducing the power consumption. Realized in 55-nm CMOS technology, the CDR consumes 15.2mW with a 1.2V supply.",

author = "Weijia Han and Yongsheng Wang and Jinxiang Wang",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 ; Conference date: 31-10-2018 Through 03-11-2018",

year = "2018",

month = dec,

day = "5",

doi = "10.1109/ICSICT.2018.8564977",

language = "英语",

series = "2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Ting-Ao Tang and Fan Ye and Yu-Long Jiang",

booktitle = "2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings",

address = "美国",

}

Han, W, Wang, Y & Wang, J 2018, A 12.5Gbps Dual Loop CDR with Multi-band VCO and Novel Frequency Band Switch. in T-A Tang, F Ye & Y-L Jiang (eds), 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings., 8564977, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018, Qingdao, China, 31/10/18. https://doi.org/10.1109/ICSICT.2018.8564977

A 12.5Gbps Dual Loop CDR with Multi-band VCO and Novel Frequency Band Switch. / Han, Weijia; Wang, Yongsheng; Wang, Jinxiang.
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings. ed. / Ting-Ao Tang; Fan Ye; Yu-Long Jiang. Institute of Electrical and Electronics Engineers Inc., 2018. 8564977 (2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 12.5Gbps Dual Loop CDR with Multi-band VCO and Novel Frequency Band Switch

AU - Han, Weijia

AU - Wang, Yongsheng

AU - Wang, Jinxiang

PY - 2018/12/5

Y1 - 2018/12/5

N2 - A novel 12.5Gbps quarter rate CDR is presented in this paper. For lock acquisition depends on the frequency tracking loop (FLL loop) and recovered clock jitter depends on the phase tracking loop (PLL loop) without one impacting the other, the CDR gets both short lock acquisition and low clock jitter. Moreover, a novel frequency band switch (FBS) is proposed, which switches the band of VCO. Meanwhile, the FBS ensures proper switching of dual loops to prevent false locking, without another lock detector, reducing the power consumption. Realized in 55-nm CMOS technology, the CDR consumes 15.2mW with a 1.2V supply.

AB - A novel 12.5Gbps quarter rate CDR is presented in this paper. For lock acquisition depends on the frequency tracking loop (FLL loop) and recovered clock jitter depends on the phase tracking loop (PLL loop) without one impacting the other, the CDR gets both short lock acquisition and low clock jitter. Moreover, a novel frequency band switch (FBS) is proposed, which switches the band of VCO. Meanwhile, the FBS ensures proper switching of dual loops to prevent false locking, without another lock detector, reducing the power consumption. Realized in 55-nm CMOS technology, the CDR consumes 15.2mW with a 1.2V supply.

UR - https://www.scopus.com/pages/publications/85060299041

U2 - 10.1109/ICSICT.2018.8564977

DO - 10.1109/ICSICT.2018.8564977

M3 - 会议稿件

AN - SCOPUS:85060299041

T3 - 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings

BT - 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings

A2 - Tang, Ting-Ao

A2 - Ye, Fan

A2 - Jiang, Yu-Long

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018

Y2 - 31 October 2018 through 3 November 2018

ER -

Han W, Wang Y, Wang J. A 12.5Gbps Dual Loop CDR with Multi-band VCO and Novel Frequency Band Switch. In Tang TA, Ye F, Jiang YL, editors, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. 8564977. (2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings). doi: 10.1109/ICSICT.2018.8564977

A 12.5Gbps Dual Loop CDR with Multi-band VCO and Novel Frequency Band Switch

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