TY - GEN
T1 - 48V-to-0.9V Regulator with Fractional Turn Transformer and Enhanced Coupling Inductor
AU - Li, Zikang
AU - Tan, Jingyang
AU - Wang, Yijie
AU - Xu, Dianguo
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - Single-stage 4 8 V-to- 0. 9 V regulated solutions for high-performance processors become increasingly popular. With the increase in DC bus voltage, the decrease in processor operating voltage, and the rise in load variation frequency, high-performance DC-DC converters with higher step-down ratios and higher loop bandwidths are in demand. This paper proposes a buck converter based on fractional turn structure and enhanced coupled inductors. The transformer achieves a higher step-down ratio using a lower number of printed circuit board (PCB) layers through series flux splitting. The secondary side employs a half-turn winding structure to reduce resistance and leakage inductance. By optimizing the layout of synchronous rectifier switches, high-current windings, and terminals, the loop configuration is optimized to minimize losses caused by parasitic inductance. A trans-inductor structure is designed based on the topology to reduce transient output inductance, and the operation mechanisms of the enhanced multiphase coupled inductor is explained. Using standard planar EI cores, a prototype operating at 500 kHz switching frequency with 48 V to 0.9 V conversion, 50 A per phase, achieves a peak efficiency of 90.3% and a current density of 0.2 A / mm2. This provides new ideas for future solutions in data centers.
AB - Single-stage 4 8 V-to- 0. 9 V regulated solutions for high-performance processors become increasingly popular. With the increase in DC bus voltage, the decrease in processor operating voltage, and the rise in load variation frequency, high-performance DC-DC converters with higher step-down ratios and higher loop bandwidths are in demand. This paper proposes a buck converter based on fractional turn structure and enhanced coupled inductors. The transformer achieves a higher step-down ratio using a lower number of printed circuit board (PCB) layers through series flux splitting. The secondary side employs a half-turn winding structure to reduce resistance and leakage inductance. By optimizing the layout of synchronous rectifier switches, high-current windings, and terminals, the loop configuration is optimized to minimize losses caused by parasitic inductance. A trans-inductor structure is designed based on the topology to reduce transient output inductance, and the operation mechanisms of the enhanced multiphase coupled inductor is explained. Using standard planar EI cores, a prototype operating at 500 kHz switching frequency with 48 V to 0.9 V conversion, 50 A per phase, achieves a peak efficiency of 90.3% and a current density of 0.2 A / mm2. This provides new ideas for future solutions in data centers.
KW - data center
KW - enhanced coupled inductor
KW - fractional-turn transformer
KW - high-efficiency DC-DC
UR - https://www.scopus.com/pages/publications/105033236412
U2 - 10.1109/ITECAsia-Pacific63742.2025.11344952
DO - 10.1109/ITECAsia-Pacific63742.2025.11344952
M3 - 会议稿件
AN - SCOPUS:105033236412
T3 - Proceedings of the 2025 IEEE Transportation Electrification Conference and Expo, Asia-Pacific, ITEC Asia-Pacific 2025
BT - Proceedings of the 2025 IEEE Transportation Electrification Conference and Expo, Asia-Pacific, ITEC Asia-Pacific 2025
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2025 IEEE Transportation Electrification Conference and Expo, Asia-Pacific, ITEC Asia-Pacific 2025
Y2 - 25 November 2025 through 28 November 2025
ER -