考虑器件结构布局的功率循环失效模式分离机制

Power cycling test is considered as the most important reliability test and widely used to evaluate the long-term reliability of package of power electronics. More and more factors are considered in the lifetime model to improve its accuracy; for example the device parameters are also included in CIPS08 model. However, the challenge is the failure modes separation and failure mechanism based on the lifetime models. In this paper, the separation mechanism of the power cycling induced failure mode was pointed out with the consideration of geometry layout rather than the test conditions. The difference in the thermal stress and failure mechanism, caused by different geometry layout, was also researched to give the guidance for package design. EasyPACK full bridge module with 6 switches (FS25R12W1T4) from INFINEON was selected for testing. Focusing on the IGBT switches (S₂ and S₃) with different IGBT chip and direct copper bonded (DCB) area ratios, the power cycling tests were performed under the same test conditions (ΔT_j≈90K and T_jmax≈150℃). The IGBT switch (S₃) with small area ratio showed the bond wire failure and the one with big area ratio with the chip solder layer degradation. This indicated that the small area ratio with larger thermal dissipation path can reduce the temperature gradient and thermal stress of the chip solder; then the bond wire becomed the weak point and finally failed. Furthermore, additional power cycling tests were also performed to verify the failure mode separation. Finally, the finite element model of FS25R12W1T4 was built to analyse the temperature distribution of the chip solder and explain the failure mechanism.